Is P is subset of NP?

 Answer: A

P is a subset of NP. P problems are decidable in polynomial time, and NP problems are verifiable in polynomial time. A problem that is decidable in polynomial time is also verifiable in polynomial time.

NP is not a subset of NP-hard. NP-hard problems are at least as hard as any NP problem, meaning that there is no efficient algorithm that can solve them in polynomial time.

NP-complete problems are a subset of NP-hard problems and are the hardest problems in NP. NP-complete problems can be verified in polynomial time.

 Answer: A

P is a subset of NP. P problems are decidable in polynomial time, and NP problems are verifiable in polynomial time. A problem that is decidable in polynomial time is also verifiable in polynomial time.

NP is not a subset of NP-hard. NP-hard problems are at least as hard as any NP problem, meaning that there is no efficient algorithm that can solve them in polynomial time.

NP-complete problems are a subset of NP-hard problems and are the hardest problems in NP. NP-complete problems can be verified in polynomial time.

Sorting algorithms can also be characterized as

Answer:  A

Sorting algorithms can also be characterized as simple or sophisticated. 

Simple algorithms require the O (n^2) comparisons to sort n items.

While sophisticated algorithms require the O (log₂n) comparisons to sort n items.

 

Answer:  A

Sorting algorithms can also be characterized as simple or sophisticated. 

Simple algorithms require the O (n^2) comparisons to sort n items.

While sophisticated algorithms require the O (log₂n) comparisons to sort n items.

 

Which of the following is true regarding referential integrity?

 

Answer: every foreign-key value must match a primary-key value in an associated table

Referential integrity constraint refers to the relationship between the tables.

The relationship between tables is maintained using foreign keys.

Referential integrity constraint states that a foreign key must have a matching primary key in associated table or must be null.

Referential Integrity constraint prevents entering a row in the child table (where you have the foreign key) for which you don't have any corresponding row in the parent table (primary key).

 

Answer: every foreign-key value must match a primary-key value in an associated table

Referential integrity constraint refers to the relationship between the tables.

The relationship between tables is maintained using foreign keys.

Referential integrity constraint states that a foreign key must have a matching primary key in associated table or must be null.

Referential Integrity constraint prevents entering a row in the child table (where you have the foreign key) for which you don't have any corresponding row in the parent table (primary key).

Which IP address class belongs to multicast?

 

Answer: Class D

An IPv4 address can be divided into five classes in classful IP addressing as follows:

• Class A
• Class B
• Class C
• Class D
• Class E

Class A: In 32 bits, the first 8 bits are for the network part, and the remaining 24 bits are reserved for the host part of the address. The leading first bit of the octet is fixed as ‘0’.

Network addresses: 2⁷−2 = 12627−2 = 126 usable addresses

Host addresses: 2²⁴−2 = 16,777,214224−2 = 16,777,214 usable addresses

Class B: In 32 bits, the first 16 bits are for the network part , and the remaining 16 bits are reserved for the host part of the address. The leading first two bits of the octet are fixed as ‘01’.

Network addresses: 2¹⁴ = 16384214 = 16384 usable addresses

Host addresses: 2¹⁶–2 = 65534216–2 = 65534 usable addresses

Class C: In 32 bits, the first 24 bits are for the network part , and the remaining 8 bits are reserved for the host part of the address. The leading first three bits of the octet are fixed as ‘110’.

Network addresses: 2²¹ = 2097152221 = 2097152 usable addresses

Host addresses: 2⁸–2 = 25428–2 = 254 usable addresses

Class D: Reserved for multicasting. Higher-order bits of the octet are set as ‘1110’.

Class E: Reserved for experiment and research purposes. Higher-order bits of the octet are set as ‘1111’.

The issue with IPv4 classful addressing is that thousands of addresses are wasted in Class A, few in Class B. Class C has few addresses which are not sufficient.

To overcome these issues Classless Inter-Domain Routing (CIDR) has taken the place of classful addressing.

 

 

Answer: Class D

An IPv4 address can be divided into five classes in classful IP addressing as follows:

• Class A
• Class B
• Class C
• Class D
• Class E

Class A: In 32 bits, the first 8 bits are for the network part, and the remaining 24 bits are reserved for the host part of the address. The leading first bit of the octet is fixed as ‘0’.

Network addresses: 2⁷−2 = 12627−2 = 126 usable addresses

Host addresses: 2²⁴−2 = 16,777,214224−2 = 16,777,214 usable addresses

Class B: In 32 bits, the first 16 bits are for the network part , and the remaining 16 bits are reserved for the host part of the address. The leading first two bits of the octet are fixed as ‘01’.

Network addresses: 2¹⁴ = 16384214 = 16384 usable addresses

Host addresses: 2¹⁶–2 = 65534216–2 = 65534 usable addresses

Class C: In 32 bits, the first 24 bits are for the network part , and the remaining 8 bits are reserved for the host part of the address. The leading first three bits of the octet are fixed as ‘110’.

Network addresses: 2²¹ = 2097152221 = 2097152 usable addresses

Host addresses: 2⁸–2 = 25428–2 = 254 usable addresses

Class D: Reserved for multicasting. Higher-order bits of the octet are set as ‘1110’.

Class E: Reserved for experiment and research purposes. Higher-order bits of the octet are set as ‘1111’.

The issue with IPv4 classful addressing is that thousands of addresses are wasted in Class A, few in Class B. Class C has few addresses which are not sufficient.

To overcome these issues Classless Inter-Domain Routing (CIDR) has taken the place of classful addressing.

 

"Diamonds" represents ............. in an Entity - relationship diagram.

 

Answer: Realtionship sets

 

Answer: Realtionship sets

Consider a Schema R(A,B,C,D) and FD's A --> B and C --> D. Then the decomposition R1(A,B) and R2(C,D) is ....

Answer: dependency preserving but not lossless join

Decomposition of R into R1 and R2 is lossless-join decomposition if at least one of the following functional dependencies is in F+ (Closure of FD’s)

R1 ∩ R2 → R1

             OR

            R1 ∩ R2 → R2

Given relation R(A, B, C, D) is decomposed into R1 (A, B) and R2(C, D), and R1 ∩ R2 is empty. So, the decomposition is not lossless.

Decomposition of R into R1 and R2 is a dependency preserving decomposition if closure of functional dependencies after decomposition is same as closure of of FDs before decomposition.

In given relation R, the FD’s A->B and C->D are preserved after decomposition also.

Refer Properties of Relational decomposition

Answer: dependency preserving but not lossless join

Decomposition of R into R1 and R2 is lossless-join decomposition if at least one of the following functional dependencies is in F+ (Closure of FD’s)

R1 ∩ R2 → R1

             OR

            R1 ∩ R2 → R2

Given relation R(A, B, C, D) is decomposed into R1 (A, B) and R2(C, D), and R1 ∩ R2 is empty. So, the decomposition is not lossless.

Decomposition of R into R1 and R2 is a dependency preserving decomposition if closure of functional dependencies after decomposition is same as closure of of FDs before decomposition.

In given relation R, the FD’s A->B and C->D are preserved after decomposition also.

Refer Properties of Relational decomposition

The usefulness of signals as a IPC mechanism is limited because ...........

 

Answer: they cannot carry information directly.

Signals are useful in inter process communication (IPC) in a limited way. They are system messages that are sent from one process to another. Signals are not used to transfer data but are used for remote commands between processes.

One of the methods of IPC is using signals, which are asynchronous notifications sent to a process by the operating system, another process, or itself.

Signals can be used to inform a process about different events, such as user input, termination, suspension, or errors.

One of the main advantages of using signals for IPC is that they are simple and efficient. Signals do not require any data structures, buffers, or queues to store or transmit information.

One of the main disadvantages of using signals is that they are unreliable and unpredictable.

Refer Interprocess communication

 

Answer: they cannot carry information directly.

Signals are useful in inter process communication (IPC) in a limited way. They are system messages that are sent from one process to another. Signals are not used to transfer data but are used for remote commands between processes.

One of the methods of IPC is using signals, which are asynchronous notifications sent to a process by the operating system, another process, or itself.

Signals can be used to inform a process about different events, such as user input, termination, suspension, or errors.

One of the main advantages of using signals for IPC is that they are simple and efficient. Signals do not require any data structures, buffers, or queues to store or transmit information.

One of the main disadvantages of using signals is that they are unreliable and unpredictable.

Refer Interprocess communication

In a two pass assembler the object code generation is done during the ..............

 

Answer: second pass

An assembler is responsible for translating low-level assembly code into relocatable machine code and creating data for the loader.

In Two-pass assembler, on the first pass check the syntax of statements and construct a table of symbols , while on the second pass it actually translates program statements into machine language(object code).

PASS1 reads the characters from the source code and inserts labels and their values into the symbol table.

PASS2 reads the characters from the source listing and generates machine code, which is put into the object code

 

Answer: second pass

An assembler is responsible for translating low-level assembly code into relocatable machine code and creating data for the loader.

In Two-pass assembler, on the first pass check the syntax of statements and construct a table of symbols , while on the second pass it actually translates program statements into machine language(object code).

PASS1 reads the characters from the source code and inserts labels and their values into the symbol table.

PASS2 reads the characters from the source listing and generates machine code, which is put into the object code

if an array is used as a function argument the array is passed by...........

Answer: by reference

When an array (variable) is passed as a function argument, it passes the base address of the array. The base address is the location of the first element of the array in the memory.

When a function receives the array pointer, it can then access all of the elements in the array by using pointer arithmetic and dereferencing

Answer: by reference

When an array (variable) is passed as a function argument, it passes the base address of the array. The base address is the location of the first element of the array in the memory.

When a function receives the array pointer, it can then access all of the elements in the array by using pointer arithmetic and dereferencing

When the process requests for a DMA transfer

Answer: process is temporarily suspended & another process gets executed

Direct memory access (DMA) is a technique that allows an input/output (I/O) device to send to or receive data directly from the main memory, bypassing the CPU to speed up memory operations.

With DMA, the CPU can process other tasks while data transfer is being performed. The transfer of data is first initiated by the CPU.

DMA controller (DMAC) is a control unit, part of I/O device’s interface circuit, which can transfer blocks of data between I/O devices and main memory with minimal intervention from the processor.

The process requesting the DMA transfer is paused and the operation is performed, meanwhile another process is run on the processor.

The data can be transferred to and from memory by the DMAC in three ways.

In burst mode, the system bus is released only after the data transfer is completed.

In cycle stealing mode, during the transfer of data between the DMA channel and I/O device, the system bus is relinquished for a few clock cycles so that the CPU can perform other tasks. When the data transfer is complete, the CPU receives an interrupt request from the DMA controller.

In transparent mode, the DMAC can take charge of the system bus only when it is not required by the processor.

Answer: process is temporarily suspended & another process gets executed

Direct memory access (DMA) is a technique that allows an input/output (I/O) device to send to or receive data directly from the main memory, bypassing the CPU to speed up memory operations.

With DMA, the CPU can process other tasks while data transfer is being performed. The transfer of data is first initiated by the CPU.

DMA controller (DMAC) is a control unit, part of I/O device’s interface circuit, which can transfer blocks of data between I/O devices and main memory with minimal intervention from the processor.

The process requesting the DMA transfer is paused and the operation is performed, meanwhile another process is run on the processor.

The data can be transferred to and from memory by the DMAC in three ways.

In burst mode, the system bus is released only after the data transfer is completed.

In cycle stealing mode, during the transfer of data between the DMA channel and I/O device, the system bus is relinquished for a few clock cycles so that the CPU can perform other tasks. When the data transfer is complete, the CPU receives an interrupt request from the DMA controller.

In transparent mode, the DMAC can take charge of the system bus only when it is not required by the processor.